It is known to protect a circuit such as an integrated circuit from damage from electrostatic discharges (ESDs). Many of these known techniques, however, do not protect the circuit against input signals which create a voltage that is above the supply voltage that powers the circuit to be ESD protected.
An example of such a prior art circuit is shown in FIG. 1A, wherein an ESD protection circuit 10 provides protection at an input terminal of an inverter 12. ESD protection circuit 10 includes diodes D1 and D2, with diode D1 connected between the input terminal 14 and ground and diode D2 connected between the input terminal 14 and the positive supply voltage V.sub.CC. Inverter 12 is of a conventional CMOS structure and contains an N-channel low-side MOSFET M1 and a P-channel high-side MOSFET M2. The input signal V.sub.in is applied to the input terminal 14, and in a known manner inverter 12 produces an inverted output signal V.sub.out at output terminal 16. Diode D3 can be a diode associated with the structure whereby the MOSFETs M1 and M2 are formed, particularly the N-well in which the P-channel MOSFET M2 is formed. When integrating the circuit monolithically, diode D3 may unavoidably be formed unless the IC is produced in oxide (dielectrically) isolated processes which eliminate the junctions between the well diffusions and between the well diffusions and the underlying substrate. Thus diode D3 may be a parasitic diode or may be added to the circuit by design.
V.sub.in, and V.sub.out are shown in FIG. 1B. If V.sub.in is going from zero to V.sub.CC, then somewhere near the halfway point (V.sub.CC /2) V.sub.out swings from V.sub.CC to zero. The reverse occurs when V.sub.in travels from V.sub.CC to zero.
Since V.sub.in is normally at or below V.sub.CC, diode D1 is usually reverse-biased (although it could occasionally be zero-biased when V.sub.in, is at ground potential). Likewise, diode D2 is normally reverse-biased except in the case where V.sub.in =V.sub.CC. Diode D3 is reverse-biased so long as a V.sub.CC is present.
Inverter 12 could be any circuit to be protected, and this is made clear in FIG. 2A which shows a generic circuit 20 being protected by ESD protection circuit 12.
FIGS. 2B-2F illustrate the circuit of FIG. 2A in operation, with an ESD pulse modeled as a network 22 containing a capacitor C1 charged to some generated voltage V.sub.gen in series with a resistor R1 and a switch S1. When the switch S1 is thrown, capacitor C1 discharges through resistor R1, and an ESD pulse having a voltage of V.sub.ESD appears at the terminals of the network 22. V.sub.ESD could vary from hundreds to thousands of volts, for example. It should be noted that while VESD can reach thousands of volts, the amount of energy contained in capacitor C1 is small because the capacitance and stored charge (Q=CV) associated with an ESD pulse is relatively small.
FIGS. 2B and 2C illustrate the situation where the ESD pulse is applied between the input terminal 14 and ground. This could occur, for example, when the chip is picked up, before it is plugged into a circuit board and before it is connected to a power supply. In FIG. 2B the positive side of the ESD pulse is applied to the input terminal 14, and diode D1 breaks down to protect circuit 20, which is exposed to a voltage equal to the breakdown voltage of diode D1 (BV.sub.D1). The input to circuit 20 frequently contains a small transistor with a very thin gate oxide layer, which would be destroyed if it were exposed to the voltage surge that would be present at the input if diode D1 were not present. A current I.sub.ESD flows through diode D1 in the reverse direction. In FIG. 2C the negative side of the ESD pulse appears at input terminal 14 and circuit 20 is exposed to the forward voltage drop across diode D1 (usually in the range of 0.6-1.0 V).
In FIGS. 2D-2F the ESD pulse is applied between the input terminal 14 and the power supply V.sub.CC. FIG. 2D illustrates the situation where the positive side of the pulse is applied to the input terminal 14 and the other terminals are left floating. As shown, diode D2 is forward biased and circuit 20 is exposed to the forward voltage drop across diode D2 (0.6-1.0 V).
When the negative side of the ESD pulse is applied to the input terminal 14, two situations could occur. One possibility, shown in FIG. 2E, is that diode D2 breaks down, and the current I.sub.ESD flows through diode D2 in the reverse direction, subjecting circuit 20 to the breakdown voltage of diode D2. Alternatively, as shown in FIG. 2F, diode D3 could break down and the current I.sub.ESD could flow in the forward direction through diode D1. In such ESD tests the ground pin is assumed to be floating although in actual applications it may be connected to other circuits. The latter is the preferred discharge path if the sum of the breakdown voltage of diode D3 and the forward voltage drop across diode D1 is less than the breakdown voltage of diode D2.
Diode D3 could be part of a parasitic bipolar transistor with some type of resistive emitter to base short (see FIG. 3A). So not only is a PN junction present but a diode which, when it breaks down, causes a base current to flow and the bipolar transistor to snap back. This reduces the voltage across the device to a sustaining voltage that is below the actual breakdown voltage of the diode itself. This is favorable from the standpoint both of protecting circuit 20 from ESD and limiting the heat generated in the diode, since the current will be the same but the voltage will be less than the breakdown voltage of the diode. Diode D3 could also be a part of a MOSFET in which, by the field plate effect, the breakdown voltage of the diode is lowered (see FIG. 3B). In this case the MOSFET has to be designed such that the gate induces break down in the silicon but still is not subjected to so many hot carriers that the gate oxide itself is destroyed. Generally, the diodes shown in FIGS. 3A and 3B are part of the bipolar or MOSFET protection device, but in other arrangements additional diodes may be connected in parallel with the bipolar or MOSFET to form a current divider, thereby controlling the snapback point.
In a case where a parasitic bipolar transistor snaps back (as shown in FIG. 3C) or a MOSFET experiences field plate induced breakdown, the voltage starts out at a voltage above V.sub.CC and the current increases until it reaches a level where in the device snaps back and the voltage falls to a sustaining voltage V.sub.sustain below V.sub.CC and within a range in which the device is normally operated (the hatched area in FIG. 3C).
This mechanism could not be invoked during normal operation or else the device could blow up. Snapback during an ESD pulse is acceptable because the energy contained in the ESD pulse is relatively small. If a condition of longer duration and greater energy causes the snapback, the device will overheat and probably blow up. Thus ESD protection devices cannot survive overvoltage or overcurrent conditions stresses for prolonged intervals, despite their ability to protect against the high voltages of ESD transients.
With ESD protection circuit 10 a problem can occur in a circuit of the kind shown in FIG. 4. Here circuit 20 is powered by a V.sub.battery directly from a battery 44, while the input signal V.sub.IN is generated by a CMOS buffer stage 42 which is supplied by a DC/DC converter 40. The component in circuit 20 supplied by V.sub.IN could be, for example, a microprocessor or a custom chip which requires a precisely regulated supply voltage, while the component of circuit 20 to be protected against ESD could be another IC containing digital, analog or even power devices intended to run directly off the battery. In this scenario one would want to supply the power chip with the raw battery voltage V.sub.battery to avoid the power losses and unwanted heat generation inherent in DC/DC regulator 40 if DC/DC generator 40 were to supply power to both CMOS buffer stage 42 and circuit 20. This would typically be the case if circuit 20 were a circuit that draws high currents, such as a high-current motor drive IC or a radio frequency power amplifier used in a cell phone.
The voltage supplied to buffer stage 42 is designated V.sub.CC. The ESD diodes D1 and D2 cause no problem so long as V.sub.CC is no greater than V.sub.battery. If V.sub.battery decays, however, and DC/DC converter 40 is still able to maintain a constant output VccF then V.sub.battery may actually fall below V.sub.CC. V.sub.IN, the output of buffer 42 and the input to circuit 20, could then be above V.sub.battery and diode D2 could become forward-biased. The result could be improper circuit operation or damage to either or both of circuit 20 and buffer 42.
This malfunction is illustrated in FIGS. 5A and 5B. FIG. 5A shows V.sub.battery falling over time from 4.2 V to a level which is below the V.sub.CC generated by DC/DC converter 40, which is assumed here to be 3.3 V. As shown in FIG. 5B, as soon as V.sub.battery falls below V.sub.CC, a small leakage current (I.sub.IN) begins to flow from buffer stage 42 and through diode D2. When V.sub.battery reaches about 2.7 V, diode D2 becomes fully conductive and clamps V.sub.battery at 2.7 V. I.sub.IN then begins to rise rapidly. Depending on the output filter capacitance and the energy stored in DC/DC converter 40, several scenarios could occur. If there is enough capacitance, the current could continue to rise rapidly (curve a) and the diode D2 could fail. The current could be somehow limited (curve b), e.g., by series resistance, so that it would continue to flow through diode D2 for some period of time until the V.sub.battery continues to decay and V.sub.CC is driven out of regulation. Or, the battery 44 could have so much resistance that in fact the whole system begins to fail and the current begins to decline.
Accordingly, there is a need for an ESD protection circuit which does not conduct when the input voltage rises to a level substantially above the supply voltage or falls to a level substantially below ground.